UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 13

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 17 MULTIPLIER/DIVIDER ................................................................................................... 713
CHAPTER 18 DMA CONTROLLER ..................................................................................................... 722
CHAPTER 19 INTERRUPT FUNCTIONS.............................................................................................. 745
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
16.8 Supplying LCD Drive Voltages V
16.9 Selection of LCD Display Data ................................................................................................ 711
17.1 Functions of Multiplier/Divider................................................................................................ 713
17.2 Configuration of Multiplier/Divider ......................................................................................... 713
17.3 Register Controlling Multiplier/Divider................................................................................... 718
17.4 Operations of Multiplier/Divider.............................................................................................. 719
18.1 Functions of DMA Controller .................................................................................................. 722
18.2 Configuration of DMA Controller ............................................................................................ 723
18.3 Registers Controlling DMA Controller ................................................................................... 726
18.4 Operation of DMA Controller................................................................................................... 729
18.5 Example of Setting of DMA Controller ................................................................................... 730
18.6 Cautions on Using DMA Controller ........................................................................................ 743
19.1 Interrupt Function Types ......................................................................................................... 745
19.2 Interrupt Sources and Configuration ..................................................................................... 746
19.3 Registers Controlling Interrupt Functions............................................................................. 751
19.4 Interrupt Servicing Operations ............................................................................................... 769
16.7.1 Static display example................................................................................................................. 692
16.7.2 Two-time-slice display example .................................................................................................. 695
16.7.3 Three-time-slice display example ................................................................................................ 698
16.7.4 Four-time-slice display example .................................................................................................. 702
16.7.5 Eight-time-slice display example ................................................................................................. 705
16.8.1 External resistance division method ............................................................................................ 708
16.8.2 Internal voltage boosting method ................................................................................................ 709
16.8.3 Capacitor split method................................................................................................................. 710
16.9.1 A-pattern area and B-pattern area data display .......................................................................... 711
16.9.2 Blinking display (Alternately displaying A-pattern and B-pattern area data) ................................ 712
17.4.1 Multiplication operation................................................................................................................ 719
17.4.2 Division operation........................................................................................................................ 720
18.4.1 Operation procedure ................................................................................................................... 729
18.4.2 Transfer mode ............................................................................................................................. 730
18.4.3 Termination of DMA transfer ....................................................................................................... 730
18.5.1 CSI consecutive transmission ..................................................................................................... 730
18.5.2 CSI master reception................................................................................................................... 732
18.5.3 CSI transmission/reception ......................................................................................................... 734
18.5.4 Consecutive capturing of A/D conversion results ........................................................................ 736
18.5.5 UART consecutive reception + ACK transmission ...................................................................... 738
18.5.6 Holding DMA transfer pending by DWAITn ................................................................................. 740
18.5.7 Forced termination by software ................................................................................................... 741
19.4.1 Maskable interrupt acknowledgment ........................................................................................... 769
19.4.2 Software interrupt request acknowledgment ............................................................................... 771
19.4.3 Multiple interrupt servicing........................................................................................................... 772
19.4.4 Interrupt request hold .................................................................................................................. 775
LC0
, V
LC1
, V
LC2
, and V
LC3
.................................................... 708
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