UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 973

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Operation of
timer array
unit as
independent
channel
Operation
of plural
channels of
timer array
unit
Real-time
counter
Function
Input pulse
interval
measurement
Input signal
high-/low-level
width
measurement
PWM function
One-shot pulse
output function
Multiple PWM
output function
PER0:
Peripheral
enable register 0
RTCC0: Real-
time counter
control register 0
Details of
Function
When using the real-time counter, first set RTCEN to 1, while oscillation of the
subsystem clock (f
time counter is ignored, and, even if the register is read, only the default value is read.
If RCLOE0 and RCLOE1 are changed when RTCE = 1, the last waveform of the
32.768 kHz and 1 Hz output signals may become short.
The TIpq pin input is sampled using the operating clock selected with the CKSpq bit
of the TMRpq register, so an error equal to the number of operating clocks occurs.
The TIpq pin input is sampled using the operating clock selected with the CKSpq bit
of the TMRpq register, so an error equal to the number of operating clocks occurs.
To rewrite both TDRmn of the master channel and TDRmp of the slave channel, a
write access is necessary two times. The timing at which the values of TDRmn and
TDRmp are loaded to TCRmn and TCRmp is upon occurrence of INTTMmn of the
master channel. Thus, when rewriting is performed split before and after occurrence
of INTTMmn of the master channel, the TOmp pin cannot output the expected
waveform. To rewrite both TDRmn of the master and TDRmp of the slave, therefore,
be sure to rewrite both the registers immediately after INTTMmn is generated from
the master channel.
The timing of loading of TDRmn of the master channel is different from that of
TDRmp of the slave channel. If TDRmn and TDRmp are rewritten during operation,
therefore, an illegal waveform is output. Be sure to rewrite TDRmn and TDRmp after
INTTMmn of the channel to be rewritten is generated.
To rewrite both TDRmn of the master channel and TDRmp of the slave channel 1,
write access is necessary at least twice. Since the values of TDRmn and TDRmp
are loaded to TCRmn and TCRmp after INTTMmn is generated from the master
channel, if rewriting is performed separately before and after generation of INTTMmn
from the master channel, the TOmp pin cannot output the expected waveform. To
rewrite both TDRmn of the master and TDRmp of the slave, be sure to rewrite both
the registers immediately after INTTMmn is generated from the master channel (This
applies also to TDRmq of the slave channel 2).
Clock supply to peripheral functions except the real-time counter can be stopped in
the HALT mode when operating on the subsystem clock by setting RTCLPC of the
operation speed mode control register (OSMC) to 1. In this case, set RTCEN to 1
and bits 0 to 6 of PER0 to 0.
SUB
) is stable. If RTCEN = 0, writing to a control register of the real-
Cautions
APPENDIX C LIST OF CAUTIONS
p.322
p.326
p.330
p.337
p.344
p.355
p.355
p.356
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