UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 475

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
14.4.2 Stopping the operation by channels
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The stopping of the operation by channels is set using each of the following registers.
SOE0
SOE1
Sem
STm
•
•
(c) Serial output enable register m (SOEm) … This register is a register that is used to enable or stop
Remark
output of the serial communication operation of each channel.
Serial Channel Enable Status Register m (SEm) … This register indicates whether data
transmission/reception operation of each channel is enabled or stopped.
Serial channel stop register m (STm) … This register is a trigger register that is used to enable
stopping communication/count by each channel.
*
•
*
*
With a channel whose operation is stopped, the value of CKOmn of the Som register can be set by software.
For channel n, whose serial output is stopped, the SO1n value of the SO1 register can be set by software.
Because STmn is a trigger bit, it is cleared immediately when SEmn = 0.
For channel n, whose serial output is stopped, the SO0n value of the SO0 register can be set by software.
Figure 14-23. Each Register Setting When Stopping the Operation by Channels (1/2)
15
15
15
15
0
0
0
0
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
The Sem register is a read-only status register, whose operation is stopped by using the STm register.
: Setting disabled (fixed by hardware), 0/1: Set to 0 or 1 depending on the usage of the user
14
14
14
14
0
0
0
0
13
13
13
13
0
0
0
0
1: Clears Semn to 0 and stops the communication operation
12
12
12
12
0
0
0
0
11
11
11
11
0
0
0
0
10
10
10
10
0
0
0
0
0: Stops output by serial communication operation
0: Stops output by serial communication operation
0
0
9
9
0
0
9
9
8
0
8
0
8
0
8
0
7
0
7
0
0
0
7
7
0: Operation stops
0
0
6
6
0
0
6
6
5
0
5
0
5
0
5
0
CHAPTER 14 SERIAL ARRAY UNIT
4
0
4
0
4
0
4
0
Sem3
STm3
0/1
0/1
3
3
0
0
3
3
SOE02
SOE12
Sem2
STm2
0/1
0/1
0/1
0/1
2
2
2
2
SOE01
Sem1
STm1
0/1
0/1
0/1
1
1
1
1
0
SOE00
SOE10
STm0
Sem0
0/1
0/1
0/1
0/1
0
0
0
0
475