UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 607

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
15.5.6 Wait
data (i.e., is in a wait state).
canceled for both the master and slave devices, the next data transfer can begin.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive
Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKE = 1)
Transfer lines
Master
Slave
ACKE
SDA0
SCL0
SCL0
SCL0
IICA
IICA
H
D2
6
6
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of eighth clock
D1
7
7
Figure 15-20. Wait (1/2)
D0
8
8
Wait from slave
9
ACK
Wait after output
of ninth clock
9
FFH is written to IICA or WREL is set to 1
CHAPTER 15 SERIAL INTERFACE IICA
Wait from master
IICA data write (cancel wait)
D7
1
1
D6
2
2
D5
3
3
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