UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 558

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
14.7.1 Address field transmission
transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in
one frame.
Note To perform communication via simplified I
Remark
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Simplified I
Address field transmission is a transmission operation that first executes in I
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data level
Parity bit
Stop bit
Data direction
• Address field transmission
• Data transmission
• Data reception
• Stop condition generation
Simplified I
(V
Registers Controlling Port Function for details). When communicating with an external device with a different
potential, set the N-ch open-drain output (V
input/output pins (SCL10, SCL20) (see 4.4.4 Connecting to external device with different potential (2.5 V, 3 V)
for details).
DD
m: Unit number (m = 0, 1), n: Channel number (n = 0, 2)
tolerance) mode (POM14 = 1, POM11 = 1) by using the port output mode register 1 (POM1) (see 4.3
2
C (IIC10, IIC20) performs the following four types of communication operations.
2
C
Max. f
Channel 2 of SAU0
SCL10, SDA10
INTIIC10
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Parity error detection flag (PEFmn)
8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as R/W
control)
However, the following condition must be satisfied in each mode of I
• Max. 400 kHz (first mode)
• Max. 100 kHz (standard mode)
Forward output (default: high level)
No parity bit
Appending 1 bit (for ACK reception timing)
MSB first
CLK
/4 [MHz] (SDRmn [15:9] = 1 or more)
(See 14.7.1.)
(See 14.7.2.)
(See 14.7.3.)
(See 14.7.4.)
Note
IIC10
2
C, set the data I/O pins (SDA10, SDA20) in the N-ch open-drain output
DD
tolerance) mode (POM15 = 1, POM10 = 1) also for the clock
Channel 0 of SAU1
SCL20, SDA20
INTIIC20
f
CHAPTER 14 SERIAL ARRAY UNIT
CLK
2
C communication to identify the target for
: System clock frequency
2
C.
Note
IIC20
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