UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 549

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Reception interrupt
Here is the flow of signal processing.
<1> The wakeup signal is detected by detecting an interrupt edge (INTP0) on a pin. When the wakeup signal is
<2> When the start bit of SBF is detected, reception is started and serial data is sequentially stored in the RXD3
<3> When SBF reception has been correctly completed, start channel 7 of the timer array unit and measure the bit
<4> Calculate a baud rate error from the bit interval of sync field (SF). Stop UART3 once and adjust (re-set) the baud
<5> The checksum field should be distinguished by software. In addition, processing to initialize UART3 after the
Edge detection
R
detected, enable reception of UART3 (RXE13 = 1) and wait for SBF reception.
register (= bits 7 to 0 of the serial data register 13 (SDR13)) at the set baud rate. When the stop bit is detected,
the reception end interrupt request (INTSR3) is generated. When data of low levels of 11 bits or more is detected
as SBF, it is judged that SBF reception has been correctly completed. If data of low levels of less than 11 bits is
detected as SBF, it is judged that an SBF reception error has occurred, and the system returns to the SBF
reception wait status.
interval (pulse width) of the sync field (see 6.7.5
measurement).
rate.
checksum field is received and to wait for reception of SBF should also be performed by software.
X
D3 (input)
(INTSR3)
LIN Bus
Capture
(INTP0)
timer
Disable
Wakeup signal
<1>
frame
Enable
Figure 14-84. Reception Operation of LIN
Disable
Sync break
13-bit SBF
reception
field
<2>
<3>
Sync field
reception
SF
Enable
Operation as input signal high-/low-level width
<4>
Identification
reception
field
CHAPTER 14 SERIAL ARRAY UNIT
ID
Data filed Data filed Checksum
reception
Data
reception
Data
reception
Data
field
<5>
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