UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 256

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
5.6.7 Time required for switchover of CPU clock and main system clock
CPU clock can be switched (between the main system clock and the subsystem clock), main system clock can be
switched (between the internal high-speed oscillation clock and the high-speed system clock), and the division ratio of the
main system clock can be changed.
switchover clock for several clocks (see Table 5-6 to Table 5-9).
CKC. Whether the main system clock is operating on the high-speed system clock or internal high-speed oscillation clock
can be ascertained using bit 5 (MCS) of CKC.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
By setting bits 0 to 2, 4, and 6 (MDIV0 to MDIV2, SDIV, MCM0, CSS) of the system clock control register (CKC), the
The actual switchover operation is not performed immediately after rewriting to CKC; operation continues on the pre-
Whether the CPU is operating on the main system clock or the subsystem clock can be ascertained using bit 7 (CLS) of
When the CPU clock is switched, the peripheral hardware clock is also switched.
Internal high-speed oscillation clock
(Remarks are listed on the next page.)
Table 5-7. Maximum Number of Clocks Required in f
(f
Set Value Before Switchover
Set Value Before Switchover
(f
MAIN
MAIN
Clock A
f
f
f
MAINC
MAINC
0
1
SUBC
f
= f
= f
IH
MX
Table 5-6. Maximum Time Required for Main System Clock Switchover
IH
Clock A
Clock B
)
MCM0
)
Table 5-8. Maximum Number of Clocks Required in f
f
f
f
f
MX
MX
MX
MX
(changing the division ratio)
≥f
<f
≥f
<f
IH
IH
IH
IH
Switching directions
f
SUBC
1 + f
2f
1 + f
↔f
MX
/f
B
MX
SUBC
IH
/f
/f
A
clock
IH
clock
clock
(changing the division ratio)
(f
Clock A
MAIN
0
= f
IH
Set Value After Switchover
Set Value After Switchover
)
MAINC
Clock B
f
f
f
MAINC
MCM0
SUBC
SUBC
f
MX
↔f
1 + f
1 + f
2f
MAINC
IH
/f
A
IH
MX
CHAPTER 5 CLOCK GENERATOR
/f
/f
(changing the division ratio),
B
MX
clock
clock
clock
(f
IH
see Table 5-7
see Table 5-8
see Table 5-9
MAIN
Clock B
↔f
1
= f
MX
Remark
MX
)
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