UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 222

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UPD78F1506GF-GAT-AX

Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet

Specifications of UPD78F1506GF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: FFFA3H
Symbol
OSTS
Remark f
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS
Figure 5-5. Format of Oscillation Stabilization Time Select Register (OSTS)
OSTS2
7
0
0
0
0
0
1
1
1
1
After reset: 07H
2. Setting the oscillation stabilization time to 20
3. To change the setting of the OSTS register, be sure to confirm that the counting
4. Do not change the value of the OSTS register during the X1 clock oscillation
5. The oscillation stabilization time counter counts up to the oscillation stabilization
6. The X1 clock oscillation stabilization wait time does not include the time until clock
X
: X1 clock oscillation frequency
register before executing the STOP instruction.
operation of the OSTC register has been completed.
stabilization time.
time set by OSTS.
In the following cases, set the oscillation stabilization time of OSTS to the value
greater than the count value which is to be checked by the OSTC register after the
oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
• If the STOP mode is entered and then released while the internal high-speed
oscillation starts (“a” below).
subsystem clock is being used as the CPU clock.
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
OSTS1
6
0
0
0
1
1
0
0
1
1
X1 pin voltage
waveform
R/W
OSTS0
5
0
0
1
0
1
0
1
0
1
STOP mode release
2
2
2
2
2
2
2
2
8
9
10
11
13
15
17
18
/f
/f
/f
/f
/f
/f
/f
/f
X
X
X
X
X
X
X
X
4
0
a
Oscillation stabilization time selection
3
0
25.6
51.2
102.4
204.8
819.2
3.27 ms
13.11 ms
26.21 ms
CHAPTER 5 CLOCK GENERATOR
f
μ
X
μ
μ
s or less is prohibited.
s
s
μ
μ
μ
OSTS2
= 10 MHz
s
s
s
2
OSTS1
Setting prohibited
25.6
51.2
102.4
409.6
1.64 ms
6.55 ms
13.11 ms
1
f
X
μ
μ
s
s
μ
μ
= 20 MHz
s
s
OSTS0
0
222

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