UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 677

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Caution For 78K0R/LF3, bits 3 and 7 must be set to 0. For 78K0R/LG3 and 78K0R/LH3, bit 7 must be set to 0.
(6)
Segment enable register (SEGEN)
SEGEN is a register that is used to enable or disable segment output to segment output only pins.
SEGEN is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets SEGEN to 00H.
Remark The segment output only pins vary, depending on the product.
PF5H
PF5L
0
1
0
1
• 78K0R/LF3: SEG8 to SEG10
• 78K0R/LG3: SEG8 to SEG14
• 78K0R/LH3: SEG8 to SEG26
Used the P54 to P57 pins as port (other than segment output)
Used the P54 to P57 pins as segment output
Used the P50 to P53 pins as port (other than segment output)
Used the P50 to P53 pins as segment output
Figure 16-6. Format of Port Function Register (PFALL) (2/2)
Port/segment outputs specification of the P54 to P57 pins
Port/segment outputs specification of P50 to P53 pins
CHAPTER 16 LCD CONTROLLER/DRIVER
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