UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 780

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
(2) Oscillation stabilization time select register (OSTS)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP
mode is released.
When the internal high-speed oscillation clock is selected as the CPU clock, confirm with OSTC that the desired
oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be
checked up to the time set using OSTC.
OSTS can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 07H.
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS before executing
Remark f
Address: FFFA3H
Symbol
OSTS
2. Setting the oscillation stabilization time to 20
3. Before changing the setting of the OSTS register, confirm that the count operation of the OSTC
4. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time.
5. The oscillation stabilization time counter counts up to the oscillation stabilization time set by
6. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation
X
: X1 clock oscillation frequency
the STOP instruction.
register is completed.
OSTS. If the STOP mode is entered and then released while the internal high-speed oscillation
clock is being used as the CPU clock, set the oscillation stabilization time as follows.
Note, therefore, that only the status up to the oscillation stabilization time set by OSTS is set to
OSTC after STOP mode is released.
starts (“a” below).
Figure 21-2. Format of Oscillation Stabilization Time Select Register (OSTS)
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by OSTS
OSTS2
7
0
0
0
0
0
1
1
1
1
After reset: 07H
OSTS1
6
0
0
0
1
1
0
0
1
1
X1 pin voltage
waveform
R/W
OSTS0
5
0
0
1
0
1
0
1
0
1
STOP mode release
2
2
2
2
2
2
2
2
8
9
10
11
13
15
17
18
/f
/f
/f
/f
/f
/f
/f
/f
X
X
X
X
X
X
X
X
4
0
a
μ
Oscillation stabilization time selection
s or less is prohibited.
3
0
25.6
51.2
102.4
204.8
819.2
3.27 ms
13.11 ms
26.21 ms
CHAPTER 21 STANDBY FUNCTION
f
X
μ
μ
s
s
μ
μ
μ
OSTS2
= 10 MHz
s
s
s
2
OSTS1
Setting prohibited
25.6
51.2
102.4
409.6
1.64 ms
6.55 ms
13.11 ms
1
f
X
μ
μ
s
s
μ
μ
= 20 MHz
s
s
OSTS0
0
780