UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 460

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03),
(6) Serial status register mn (SSRmn)
SSRmn
Symbol
SSRmn can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of SSRmn can be set with an 8-bit memory manipulation instruction with SSRmnL.
Reset signal generation clears this register to 0000H.
Note Only SSR12 register does not have FET12, PET12, and OVF12.
Remark
SSRmn is a register that indicates the communication status and error occurrence status of channel n. The errors
indicated by this register are a framing error, parity error, and overrun error.
F0140H, F0141H (SSR10), F0142H, F0143H (SSR11),
F0144H, F0145H (SSR12), F0146H, F0147H (SSR13)
Because this flag is an updating flag, it is automatically cleared when the communication operation is completed.
This flag is cleared also when the STmn/SSmn bit is set to 1.
This is an updating flag. It is automatically cleared when transfer from the SDRmn register to the shift register is
completed. During reception, it is automatically cleared when data has been read from the SDRmn register. This
flag is cleared also when the STmn/SSmn bit is set to 1.
This flag is automatically set if transmit data is written to the SDRmn register when the TXEmn bit of the SCRmn
register = 1 (transmission or reception mode in each communication mode). It is automatically set if receive data is
stored in the SDRmn register when the RXEmn bit of the SCRmn register = 1 (transmission or reception mode in
each communication mode). It is also set in case of a reception error.
If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the register is
discarded and an overrun error (OVFmn = 1) is detected.
TSF
BFF
mn
mn
15
0
1
0
1
0
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
Communication is not under execution.
Communication is under execution.
Valid data is not stored in the SDRmn register.
Valid data is stored in the SDRmn register.
14
0
Figure 14-9. Format of Serial Status Register mn (SSRmn) (1/2)
13
0
12
0
11
0
Communication status indication flag of channel n
Buffer register status indication flag of channel n
10
0
9
0
8
0
After reset: 0000H
7
0
TSF
mn
6
CHAPTER 14 SERIAL ARRAY UNIT
BFF
mn
5
R
4
0
3
0
FEF
mn
Note
2
PEF
mn
Note
1
OVF
mn
Note
0
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