UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 717

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(3) Multiplication/division data register C (MDCL, MDCH)
The MDCH and MDCL registers store remainder value of the operation result in the division mode. They are not
used in the multiplication mode.
MDCH and MDCL can be read by a 16-bit manipulation instruction.
Reset signal generation clears these registers to 0000H.
Caution The MDCH and MDCL values read during division operation processing (while the
Remark
The register configuration differs between when multiplication is executed and when division is executed, as follows.
• Register configuration during multiplication
• Register configuration during division
Address: F00E0H, F00E1H, F00E2H, F00E3H
Symbol
MDCH
Symbol
MDCL
MDAL (bits 15 to 0) × MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)]
[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ÷ [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] =
[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ⋅⋅⋅ [MDCH (bits 15 to 0), MDCL (bits 15 to 0)]
DIVMODE
<Multiplier A>
0
1
MDCH
MDCL
multiplication/division control register (MDUC) is 81H) will not be guaranteed.
DIVMODE: Bit 7 of the multiplication/division control register (MDUC)
15
15
Figure 17-4. Format of Multiplication/Division Data Register C (MDCH, MDCL)
MDCH
MDCL
Table 17-4. Functions of MDCH and MDCL During Operation Execution
14
14
<Dividend>
<Quotient>
Multiplication mode
Division mode
MDCH
MDCL
13
13
<Multiplier B>
Operation Mode
MDCH
MDCL
12
12
F00E3H
F00E1H
MDCH
MDCL
11
11
MDCH
MDCL
10
10
After reset: 0000H, 0000H R
MDCH
MDCL
9
9
MDCH
MDCL
8
8
Setting
<Remainder>
<Divisor>
−
−
MDCH
MDCL
<Product>
7
7
MDCH
MDCL
6
6
CHAPTER 17 MULTIPLIER/DIVIDER
MDCH
MDCL
5
5
MDCH: Remainder (higher 16 bits)
MDCL: Remainder (lower 16 bits)
MDCH
MDCL
4
4
F00E2H
F00E0H
MDCH
MDCL
Operation Result
3
3
MDCH
MDCL
2
2
−
MDCH
MDCL
1
1
MDCH
MDCL
0
0
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