UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 600

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(6) IICA low-level width setting register (IICWL)
(7) IICA high-level width setting register (IICWH)
(8) Port mode register 6 (PM6)
This register is used to set the low-level width of the SCL0 pin signal that is output by serial interface IICA.
The IICWL register can be set by an 8-bit memory manipulation instruction.
Set the IICWL register while operation of I
Reset signal generation sets this register to FFH.
This register is used to set the high-level width of the SCL0 pin signal that is output by serial interface IICA.
The IICWH register can be set by an 8-bit memory manipulation instruction.
Set the IICWH register while operation of I
Reset signal generation sets this register to FFH.
This register sets the input/output of port 6 in 1-bit units.
When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, clear PM60 and PM61, and
the output latches of P60 and P61 to 0.
Set IICE (bit 7 of IICA control register 0 (IICCTL0)) to 1 before setting the output mode because the P60/SCL0 and
P61/SDA0 pins output a low level (fixed) when IICE is 0.
PM6 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Symbol
Address: FFF26H
Remark
PM6
Figure 15-11. Format of IICA High-Level Width Setting Register (IICWH)
Figure 15-10. Format of IICA Low-Level Width Setting Register (IICWL)
Address: F0232H
Address: F0233H
PM6n
7
1
For how to set the transfer clock by using the IICWL and IICWH registers, see 15.4.2 Setting
transfer clock by using IICWL and IICWH registers.
0
1
Symbol
Symbol
IICWH
IICWL
After reset: FFH
Output mode (output buffer on)
Input mode (output buffer off)
Figure 15-12. Format of Port Mode Register 6 (PM6)
6
1
7
7
After reset: FFH R/W
After reset: FFH R/W
6
6
1
5
2
2
C is disabled (bit 7 (IICE) of IICA control register 0 (IICCTL0) is 0).
R/W
C is disabled (bit 7 (IICE) of IICA control register 0 (IICCTL0) is 0).
P6n pin I/O mode selection (n = 0, 1)
5
5
1
4
4
4
3
3
3
1
CHAPTER 15 SERIAL INTERFACE IICA
2
2
2
1
1
1
PM61
0
0
1
PM60
0
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