UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 793

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
generated.
voltage detection or execution of illegal instruction
and 22-2. Each pin is high impedance during reset signal generation or during the oscillation stabilization time just after a
reset release, except for P130, which is low-level output.
input to the RESET pin and program execution is started with the internal high-speed oscillation clock after reset
processing. A reset by the watchdog timer is automatically released, and program execution starts using the internal high-
speed oscillation clock (see Figures 22-2 to 22-4) after reset processing. Reset by POC and LVI circuit power supply
detection is automatically released when V
internal high-speed oscillation clock (see CHAPTER 23
VOLTAGE DETECTOR) after reset processing.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The following five operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage of the low-voltage detector (LVI) or input voltage (EXLVI) from
(5) Internal reset by execution of illegal instruction
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is
A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI circuit
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is
Note
Cautions 1. For an external reset, input a low level for 10
Remark V
external input pin, and detection voltage
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
V
2. During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and internal
3. When the STOP mode is released by a reset, the RAM contents in the STOP mode are held during
4. When reset is effected, port pin P140 is set to low-level output and other port pins become high-
POR
LVI
(To perform an external reset upon power application, a low level of at least 10
continued during the period in which the supply voltage is within the operating range (V
V)).
low-speed oscillation clock stop oscillating. External main system clock input becomes invalid.
reset input.
impedance, because each SFR and 2nd SFR are initialized.
:
: POC power supply rise detection voltage
LVI detection voltage
CHAPTER 22 RESET FUNCTION
DD
≥ V
POR
Note
, and each item of hardware is set to the status shown in Tables 22-1
or V
Note
DD
≥ V
POWER-ON-CLEAR CIRCUIT and CHAPTER 24
LVI
μ
s or more to the RESET pin
after the reset, and program execution starts using the
CHAPTER 22 RESET FUNCTION
μ
s must be
DD
LOW-
≥ 1.8
793