UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 309

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
Remark mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with timer I/O pins)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Figure 6-39. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/3)
(2) When the timer input (TIpq pin input, f
TMRmn
TPSm
TOp
Note The timer input is selected by using TISpq bit, SDIV bit, and RTCISpq bit.
(a) Timer mode register mn (TMRmn)
(b) Timer clock select register m (TPSm)
(c) Timer output register p (TOp)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
Figure 6-17 Format of Timer Input Select Registers 0, 1 (TIS0, TIS1).
Bits 7 to 4, 3 to 0
PRSmk3 to PRSmk0
CKSmn
TOpq
Bit q
1/0
1/0
15
0000
Operation clock selection
14
0: Selects CKm0 as operation clock of channel n.
1: Selects CKm1 as operation clock of channel n.
f
0
CLK
(no division) is selected as selected operation clock by TPSm register.
0: Outputs 0 from TOpq.
1: Outputs 1 from TOpq.
13
0
0000B: Selects f
k = 0 (bits 0 to 3) when CKm0 is selected and k = 1 (bits 4 to 7) when CKm1 is selected
CCSmn
12
1
Count clock selection
TERmn
MAS
11
1: Selects timer input valid edge.
0
CLK
Slave/master selection
STSmn2
10
0: Cleared to 0 when independent function is selected.
(no division) as operation clock selected by CKSmn of TMRmn register.
0
SUB
STSmn1
/4, f
0
9
SUB
Start trigger selection
STSmn0
/2 or INTRTCI) is selected as count clock
000B: Selects only software start.
8
0
CISmn1
1/0
7
CISmn0
1/0
6
Selection of edge of timer input
00B: detects falling edge.
01B: detects rising edge.
10B: detects both edges.
11B: Setting prohibited
Operation mode of channel n
000B: Interval timer
5
0
Setting of operation when counting is started
CHAPTER 6 TIMER ARRAY UNIT
0: Neither generates INTTMmn nor inverts
1: Generates INTTMmn and inverts timer
timer output when counting is started.
output when counting is started.
4
0
MDmn3
3
0
MDmn2
2
0
For details, refer to
Note
MDmn1
1
0
(1/2)
MDmn0
1/0
0
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