UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 609

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
15.5.7 Canceling wait
0 (IICCTL0) to 1.
output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IICA.
that the wait state can be canceled.
so that the wait state can be canceled.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The I
• Writing data to IICA shift register (IICA)
• Setting bit 5 (WREL) of IICA control register 0 (IICCTL0) (canceling wait)
• Setting bit 1 (STT) of IICCTL0 register (generating start condition)
• Setting bit 0 (SPT) of IICCTL0 register (generating stop condition)
When the above wait canceling processing is executed, the I
To cancel a wait state and transmit data (including addresses), write the data to IICA.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL) of IICA control register
To generate a restart condition after canceling a wait state, set bit 1 (STT) of IICCTL0 to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT) of IICCTL0 to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to IICA after canceling a wait state by setting WREL to 1, an incorrect value may be
In addition to the above, communication is stopped if IICE is cleared to 0 when communication has been aborted, so
If the I
Caution If a processing to cancel a wait state executed when WUP (bit 7 of IICA control register 1 (IICCTL1)) =
Note Master only
2
C usually cancels a wait state by the following processing.
2
C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL) of IICCTL0,
1, the wait state will not be canceled.
2
C cancels the wait state and communication is resumed.
Note
Note
CHAPTER 15 SERIAL INTERFACE IICA
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