UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 560

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(2) Operation procedure
Caution
After setting the SAUmEN to 1, be sure to set the SPSm register after 4 or more clocks have
elapsed.
Changing setting of SOEm register
Setting SMRmn register
Setting SCRmn register
Setting SDRmn register
Starting communication
Writing to SSm register
Setting SPSm register
Setting PER0 register
Starting initial setting
Setting SOm register
Setting SOm register
Setting SOm register
Figure 14-89. Initial Setting Procedure for Address Field Transmission
Setting port
Wait
Release the serial array unit from the
reset status and start clock supply.
Enable data output, clock output, and the N-ch
open-drain output (V
target channel by setting a port register, a port
mode register, and a port output mode register.
Set the prescaler.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate.
Manipulate the SOmn and CKOmn bits
and set an initial output level.
Clear the SOmn bit to 0 to generate the
start condition.
Secure a wait time so that the specifications of
I
Clear the CKOmn bit to 0 to lower the
clock output level.
Set the SOEmn bit to 1 and enable data
output of the target channel.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set address and R/W to the SIOr register
(bits 7 to 0 of the SDRmn register) and
start communication.
2
C on the slave side are satisfied.
DD
tolerance) mode of the
CHAPTER 14 SERIAL ARRAY UNIT
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