UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 782

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UPD78F1506GF-GAT-AX

Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet

Specifications of UPD78F1506GF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
<R>
78K0R/Lx3
Remarks 1.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Item
System clock
CPU
Flash memory
RAM
Port (latch)
Timer array unit (TAU)
Real-time counter (RTC)
Watchdog timer
Clock output/buzzer output
A/D converter
D/A converter
Operational amplifier
Voltage reference
Serial array unit (SAU)
Serial interface (IICA)
LCD controller/driver
Multiplier/divider
DMA controller
Power-on-clear function
Low-voltage detection function
External interrupt
Key interrupt
Main system clock
Subsystem clock
f
IL
2.
HALT Mode Setting
f
f
f
The functions mounted depend on the product. Refer to 1.4
Functions.
IH
X
XT
:
: Internal high-speed oscillation clock,
: XT1 oscillation clock,
X1 oscillation clock,
f
f
f
f
IH
X
EX
XT
Clock supply to the CPU is stopped
Operation continues (cannot
be stopped)
Status before HALT mode
was set is retained
Status before HALT mode was set is retained
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Oscillates
• WTON = 1 and WDSTBYON = 0: Stops
Operation stopped
Operation stopped
Status before HALT mode was set is retained at voltage higher than POC detection voltage.
Status before HALT mode was set is retained
Operable
Set by bits 0 (WDSTBYON) and 4 (WTON) of option byte (000C0H)
• WTON = 0: Stops
• WTON = 1 and WDSTBYON = 1: Operates
• WTON = 1 and WDSTBYON = 0: Stops
Operable
When CPU Is Operating on
Oscillation Clock (f
MHz Internal High-Speed
Table 21-1. Operating Statuses in HALT Mode (1/3)
Oscillation Clock (f
Internal High-Speed
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock
IH
) or 20
IH20
)
Status before HALT mode was set is retained
Operation continues (cannot
be stopped)
Cannot operate
f
f
f
IH20
EX
IL
When CPU Is Operating on
:
:
:
X1 Clock (f
20 MHz internal high-speed oscillation clock
External main system clock
Internal low-speed oscillation clock
X
CHAPTER 21 STANDBY FUNCTION
)
Block Diagram and 1.5
Cannot operate
Operation continues (cannot
be stopped)
External Main System Clock
When CPU Is Operating on
(f
EX
)
Outline of
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