UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 289

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
• 78K0R/LF3
• 78K0R/LG3
• 78K0R/LH3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F01BEH, F01BFH
Address: F01BEH, F01BFH
Address: F01BEH, F01BFH
Address: F01E6H, F01E7H
(12) Timer output mode register p (TOMp)
Symbol
Symbol
Symbol
Symbol
TOM0
TOM0
TOM0
TOM1
(Remark is listed on the next page.)
Cautions 1. For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOM0 to “0”.
TOMp is used to control the timer output mode of each channel.
When a channel is used for the combination operation function (PWM output, one-shot pulse output, or multiple
PWM output), set the corresponding bit of the slave channel to 1.
The setting of each channel q by this register is reflected at the timing when the timer output signal is set or reset
while the timer output is enabled (TOEpq = 1).
TOMp can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of TOMp can be set with an 8-bit memory manipulation instruction with TOMpL.
Reset signal generation clears this register to 0000H.
TOM
pq
15
15
15
15
0
1
0
0
0
0
2. For 78K0R/LG3, be sure to clear bits 15 to 8 of TOM0 to “0”.
3. For 78K0R/LH3, be sure to clear bit 15 to 8 of TOM0, bits 15 to 4 of TOM1 to “0”.
Toggle mode (to produce toggle output by timer interrupt request signal (INTTMpq))
Combination operation mode (set by the timer interrupt request signal (INITTMpq) of the master channel,
and reset by the timer interrupt request signal (INITTMpr) of the slave channel)
14
14
14
14
0
0
0
0
After reset: 0000H
After reset: 0000H
After reset: 0000H
After reset: 0000H
Figure 6-21. Format of Timer Output Mode Register p (TOMp)
13
13
13
13
0
0
0
0
12
12
12
12
0
0
0
0
11
11
11
11
0
0
0
0
R/W
R/W
R/W
R/W
10
10
10
10
0
0
0
0
Control of timer output mode of channel q
9
0
9
0
9
0
9
0
8
0
8
0
8
0
8
0
TOM
TOM
TOM
07
07
07
7
7
7
7
0
TOM
TOM
06
06
6
0
6
6
6
0
TOM
TOM
05
05
CHAPTER 6 TIMER ARRAY UNIT
5
0
5
5
5
0
TOM
TOM
TOM
04
04
04
4
4
4
4
0
TOM
TOM
TOM
TOM
03
03
03
13
3
3
3
3
TOM
TOM
TOM
TOM
02
02
02
12
2
2
2
2
TOM
TOM
TOM
TOM
01
01
01
11
1
1
1
1
TOM
TOM
TOM
TOM
00
00
00
10
0
0
0
0
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