UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 391

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
9.4 Operations of Clock Output/Buzzer Output Controller
9.4.1 Operation as output pin
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(2) Port mode register 3 (PM3)
One pin can be used to output a clock or buzzer sound.
Two output pins, PCLBUZ0 and PCLBUZ1, are available.
PCLBUZ0 outputs a clock/buzzer selected by clock output select register 0 (CKS0).
PCLBUZ1 outputs a clock/buzzer selected by clock output select register 1 (CKS1).
PCLBUZn is output as the following procedure.
<1> Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2, CSELn) of the clock output select register (CKSn)
<2> Set bit 7 (PCLOEn) of CKSn to 1 to enable clock/buzzer output.
Remark
Remark
This register sets port 3 input/output in 1-bit units.
When using the P31/PCLBUZ1/TI00/TO03/RTCDIV/RTCCL/INTP2 and P32/PCLBUZ0/TI01/TO01/INTP5 pins for
clock output/buzzer output, clear PM31 and PM32 and the output latches of P32 and P31 to 0.
PM3 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
of the PCLBUZn pin (output in disabled status).
Clock output
The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or
disabling clock output (PCLOEn) is switched. At this time, pulses with a narrow width are not output. Figure
9-4 shows enabling or stopping output using PCLOEn and the timing of outputting the clock.
n = 0, 1
PCLOEn
Address: FFF23H
Symbol
PM3
Narrow pulses are not recognized
PM3n
Figure 9-4. Remote Control Output Application Example
7
1
0
1
1 clock elapsed
Figure 9-3. Format of Port Mode Register 3 (PM3)
After reset: FFH
Output mode (output buffer on)
Input mode (output buffer off)
6
1
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
5
1
P3n pin I/O mode selection (n = 0 to 4)
R/W
PM34
4
PM33
3
PM32
2
PM31
1
PM30
0
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