UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 612

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
15.5.12 Arbitration
communication among the master devices is performed as the number of clocks are adjusted until the data differs. This
kind of operation is called arbitration.
set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high impedance,
which releases the bus.
condition is detected, etc.) and the ALD = 1 setting that has been made by software.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
When several master devices simultaneously generate a start condition (when STT is set to 1 before STD is set to 1),
When one of the master devices loses in arbitration, an arbitration loss flag (ALD) in the IICA status register (IICS) is
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop
For details of interrupt request timing, see 15.5.8 Interrupt request (INTIICA) generation timing and wait control.
Remark
Transfer lines
Master 1
Master 2
SDA0
SDA0
SDA0
SCL0
SCL0
SCL0
STD:
STT:
Bit 1 of IICA status register (IICS)
Bit 1 of IICA control register 0 (IICCTL0)
Figure 15-21. Arbitration Timing Example
CHAPTER 15 SERIAL INTERFACE IICA
Master 1 loses arbitration
Hi-Z
Hi-Z
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