UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 384

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
8.4 Operation of Watchdog Timer
8.4.1 Controlling operation of watchdog timer
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
1.
2.
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5.
Cautions 1. When data is written to WDTE for the first time after reset release, the watchdog timer is cleared
When the watchdog timer is used, its operation is specified by the option byte (000C0H).
• Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the
• Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H) (for details, see 8.4.2
• Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H) (for
After a reset release, the watchdog timer starts counting.
By writing “ACH” to WDTE after the watchdog timer starts counting and before the overflow time set by the option
byte, the watchdog timer is cleared and starts counting again.
After that, write WDTE the second time or later after a reset release during the window open period. If WDTE is
written during a window close period, an internal reset signal is generated.
If the overflow time expires without “ACH” written to WDTE, an internal reset signal is generated.
An internal reset signal is generated in the following cases.
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to WDTE
counter starts operating after a reset release) (for details, see CHAPTER 26).
and CHAPTER 26).
details, see 8.4.3 and CHAPTER 26).
WDTON
0
1
2. If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time may be
3. The watchdog timer can be cleared immediately before the count value overflows.
<Example>
in any timing regardless of the window open time, as long as the register is written before the
overflow time, and the watchdog timer starts counting again.
different from the overflow time set by the option byte by up to 2/f
Counter operation disabled (counting stopped after reset)
Counter operation enabled (counting started after reset)
When the overflow time is set to 2
Watchdog Timer Counter
10
/f
IL
, writing “ACH” is valid up to count value 3FH.
CHAPTER 8 WATCHDOG TIMER
IL
seconds.
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