UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 396

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
10.3 Registers Used in A/D Converter
(1) Peripheral enable register 0 (PER0)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F00F0H
The A/D converter uses the following nine registers.
• Peripheral enable register 0 (PER0)
• A/D converter mode register (ADM)
• A/D converter mode register 1 (ADM1)
• Analog reference voltage control register (ADVRC)
• 12-bit A/D conversion result register (ADCR)
• 8-bit A/D conversion result register (ADCRH)
• Analog input channel specification register (ADS)
• A/D port configuration register (ADPC)
• Port mode registers 2, 15 (PM2, PM15)
Symbol
PER0
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is
not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Note 78K0R/LG3, 78K0R/LH3 only
Caution When setting the A/D converter, be sure to set ADCEN to 1 first. If ADCEN = 0, writing to a
ADCEN
RTCEN
<7>
control register of the A/D converter is ignored, and, even if the register is read, only the default
value is read.
0
1
After reset: 00H
Stops supply of input clock.
• SFR used by the A/D converter, operational amplifier, and voltage reference cannot be written.
• The A/D converter, operational amplifier, and voltage reference is in the reset status.
Supplies input clock.
• SFR used by the A/D converter can, operational amplifier, and voltage reference can be
read/written.
DACEN
Figure 10-3. Format of Peripheral Enable Register 0 (PER0)
<6>
R/W
Control of A/D converter, operational amplifier, and voltage reference input clock
ADCEN
<5>
IICAEN
<4>
Note
SAU1EN
<3>
SAU0EN
<2>
CHAPTER 10 A/D CONVERTER
TAU1EN
<1>
TAU0EN
<0>
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