UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 550

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
The length of the sync field transmitted from the master can be measured by using the external event capture operation of
the timer array unit (TAU) to calculate a baud-rate error.
external interrupt pin (INTP0) and timer array unit (TAU).
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Figure 14-85 shows the configuration of a port that manipulates reception of LIN.
The wakeup signal transmitted from the master of LIN is received by detecting an edge of an external interrupt (INTP0).
By controlling switch of port input (ISC0/ISC1), the input source of port input (RxD3) for reception can be input to the
Remark
P120/INTP0
P50/RxD3
P33/TI07
ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (See Figure 14-17.)
Figure 14-85. Port Configuration for Manipulating Reception of LIN
Output latch
Output latch
Output latch
(P120)
(P50)
(P33)
Port mode
Port mode
Port mode
Selector
Selector
(PM120)
Selector
(PM50)
(PM33)
<ISC0>
0: Selects INTP0 (P120)
1: Selects RxD3 (P50)
<ISC1>
0: Selects TI07 (P33)
1: Selects RxD3 (P50)
switch control
switch control
Port input
Port input
Selector
Selector
(ISC0)
(ISC1)
RXD3 input
CHAPTER 14 SERIAL ARRAY UNIT
INTP0 input
Channel 7 input of TAU
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