UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 775

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
19.4.4 Interrupt request hold
request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt
request hold instructions) are listed below.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
There are instructions where, even if an interrupt request is issued for them while another instruction is being executed,
• MOV PSW, #byte
• MOV PSW, A
• MOV1 PSW. bit, CY
• SET1 PSW. bit
• CLR1 PSW. bit
• RETB
• RETI
• POP PSW
• BTCLR PSW. bit, $addr8
• EI
• DI
• SKC
• SKNC
• SKZ
• SKNZ
• Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, MK0L, MK0H, MK1L, MK1H, MK2L, MK2H,
Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the
Figure 19-18 shows the timing at which interrupt requests are held pending.
Remarks 1. Instruction N: Interrupt request hold instruction
CPU processing
PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, and PR12H registers.
software interrupt activated by executing the BRK instruction causes the IE flag to be cleared.
Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction,
the interrupt request is not acknowledged.
2. Instruction M: Instruction other than interrupt request hold instruction
3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).
××IF
Instruction N
Figure 19-18. Interrupt Request Hold
Instruction M
PSW and PC saved, jump
to interrupt servicing
CHAPTER 19 INTERRUPT FUNCTIONS
Interrupt servicing
program
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