UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 322

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
6.7.4 Operation as input pulse interval measurement
time, the counter (TCRpq) is cleared to 0000H, and the INTTMpq is output. If the counter overflows at this time, the
OVFpq bit of the TSRpq register is set to 1. If the counter does not overflow, the OVFpq bit is cleared. After that, the
above operation is repeated.
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
of the TSRpq register is set to 1. However, the OVFpq bit is configured as a cumulative flag, the correct interval value
cannot be measured if an overflow occurs more than once.
trigger.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The count value can be captured at the TIpq valid edge and the interval of the pulse input to TIpq can be measured.
The pulse interval can be calculated by the following expression.
TCRpq operates as an up counter in the capture mode.
When the channel start trigger (TSpq) is set to 1, TCRpq counts up from 0000H in synchronization with the count clock.
When the TIpq pin input valid edge is detected, the count value is transferred (captured) to TDRpq and, at the same
As soon as the count value has been captured to the TDRpq register, the OVFpq bit of the TSRpq register is updated
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVFpq bit
Set STSpq2 to STSpq0 of the TMRpq register to 001B to use the valid edges of TIpq as a start trigger and a capture
When TEpq = 1, instead of the TIpq pin input, a software operation (TSpq = 1) can be used as a capture trigger.
Operation clock
Remark
TIpq input pulse interval = Period of count clock × ((10000H × TSRpq: OVF) + (Capture value of TDRpq + 1))
Caution The TIpq pin input is sampled using the operating clock selected with the CKSpq bit of the
TIpq pin
TMRpq register, so an error equal to the number of operating clocks occurs.
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3:
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
Figure 6-49. Block Diagram of Operation as Input Pulse Interval Measurement
CKp1
CKp0
TSpq
detection
Edge
p = 0, pq = 00 to 04, 07
Timer counter
Data register
(TCRpq)
(TDRpq)
CHAPTER 6 TIMER ARRAY UNIT
controller
Interrupt
Interrupt signal
(INTTMpq)
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