UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 976

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Watchdog
timer
Clock
output/
buzzer
output
controller
A/D
converter
Function
Setting interval
interrupt
CKSn: Clock
output select
registers n
PER0:
Peripheral
enable register 0
ADM: A/D
converter mode
register
ADM1: A/D
converter mode
register 1
ADVRC: Analog
reference
voltage control
register
ADCR: 12-bit
A/D conversion
result register
ADCRH: 8-bit
A/D conversion
result register
Details of
Function
When operating with the X1 oscillation clock after releasing the STOP mode, the
CPU starts operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer
overflow is short, an overflow occurs during the oscillation stabilization time, causing
a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization
time when operating with the X1 oscillation clock and when the watchdog timer is to
be cleared after the STOP mode release by an interval interrupt.
Change the output clock after disabling clock output (PCLOEn = 0).
If the selected clock (f
becomes undefined.
To shift to STOP mode when the main system clock is selected (CSELn = 0), set
PCLOEn = 0 before executing the STOP instruction. When the subsystem clock is
selected (CSELn = 1), PCLOEn = 1 can be set because the clock can be output in
STOP mode.
When setting the A/D converter, be sure to set ADCEN to 1 first. If ADCEN = 0,
writing to a control register of the A/D converter is ignored, and, even if the register is
read, only the default value is read.
A/D conversion must be stopped before rewriting bits ADSCM, FR0 to FR2, LV1, and
LV0 to values other than the identical data.
When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage
mode (LV1 = 1, LV0 = 0), enable the input gate voltage boost circuit for the A/D
converter by using the analog reference voltage control register (ADVRC), and then
set ADCE and ADCS to 1. After the voltage boost circuit stabilization time (10
passes after the input gate voltage boost circuit for the A/D converter has been
enabled, set ADCS to 1.
Rewriting ADM1 during A/D conversion is prohibited. Rewrite it when conversion
operation is stopped (ADCS = 0).
When using the A/D converter in normal mode 2 (LV1 = 0, LV0 = 1) or low voltage
mode (LV1 = 1, LV0 = 0), enable the input gate voltage boost circuit for the A/D
converter by using the analog reference voltage control register (ADVRC), and then
set ADCE and ADCS to 1. After the voltage boost circuit stabilization time (10
passes after the input gate voltage boost circuit for the A/D converter has been
enabled, set ADCS to 1.
To use voltage reference output to the positive reference voltage of the A/D
converter, be sure to set VRON to 1 after setting VRSEL to 1.
Do not change the output voltage of the reference voltage by using VRGV during the
voltage reference operation (VRON = 1).
When writing to A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the contents
of ADCR may become undefined. Read the conversion result following conversion
completion before writing to ADM, ADS, and ADPC. Using timing other than the
above may cause an incorrect conversion result to be read.
When writing to A/D converter mode register (ADM), analog input channel
specification register (ADS), and A/D port configuration register (ADPC), the contents
of ADCRH may become undefined. Read the conversion result following conversion
completion before writing to ADM, ADS, and ADPC. Using timing other than the
above may cause an incorrect conversion result to be read.
MAIN
or f
SUB
) stops during clock output (PCLOEn = 1), the output
Cautions
APPENDIX C LIST OF CAUTIONS
μ
s)
μ
s)
p.387
p.390
p.390
p.390
p.396
p.398
pp.398
, 399
p.400
p.401
p.402
p.402
p.402
p.403
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