UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 730

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
18.4.2 Transfer mode
data resulting from A/D conversion can be consecutively transferred, and port data can be scanned at fixed time intervals
by using a timer.
18.4.3 Termination of DMA transfer
(INTDMAn) is generated and transfer is terminated.
when transfer is terminated.
18.5 Example of Setting of DMA Controller
18.5.1 CSI consecutive transmission
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of the DMCn register.
By using these transfer modes, up to 1024 bytes of data can be consecutively transferred by using the serial interface,
When DBCn = 00H and DMA transfer is completed, the DSTn bit is automatically cleared to 0. An interrupt request
When the DSTn bit is cleared to 0 to forcibly terminate DMA transfer, the DBCn and DRAn registers hold the value
The interrupt request (INTDMAn) is not generated if transfer is forcibly terminated.
A flowchart showing an example of setting for CSI consecutive transmission is shown below.
• Consecutive transmission of CSI10
• DMA channel 0 is used for DMA transfer.
• DMA start source: INTCSI10 (software trigger (STG0) only for the first start source)
• Interrupt of CSI10 is specified by IFC03 to IFC00 (bits 3 to 0 of the DMC0 register) = 1000B.
• Transfers FFB00H to FFBFFH (256 bytes) of RAM to FFF44H of the transmit buffer (SIO10) of CSI.
Remark
DRSn
0
0
1
1
DSn
n: DMA channel number (n = 0, 1)
0
1
0
1
Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1)
Transfer from SFR of 2-byte data (fixed address) to RAM (address is incremented by +2)
Transfer from RAM of 1-byte data (address is incremented by +1) to SFR (fixed address)
Transfer from RAM of 2-byte data (address is incremented by +2) to SFR (fixed address)
DMA Transfer Mode
CHAPTER 18 DMA CONTROLLER
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