UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 470

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F0060H
(15) Noise filter enable register 0 (NFEN0)
Symbol
NFEN0
Caution Be sure to clear bits 7, 5, 3, and 1 to “0”.
NFEN0 is used to set whether the noise filter can be used for the input signal from the serial data input pin to each
channel.
Disable the noise filter of the pin used for CSI or simplified I
this register to 0.
Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to
1.
When the noise filter is enabled, CPU/peripheral operating clock (f
detection.
NFEN0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Set SNFEN30 to 1 to use the R
Clear SNFEN30 to 0 to use the P50 or SEGx pins.
Set SNFEN20 to 1 to use the R
Clear SNFEN20 to 0 to use the P11, SI20, SDA20 or INTP6 pins.
Set SNFEN10 to 1 to use the R
Clear SNFEN10 to 0 to use the P14, SI10, SDA10 or INTP4 pins.
Set SNFEN00 to 1 to use the R
Clear SNFEN00 to 0 to use the P80, SI00 or INTP9.
SNFEN30
SNFEN20
SNFEN10
SNFEN00
0
1
0
1
0
1
0
1
7
0
After reset: 00H
Noise filter OFF
Noise filter ON
Noise filter OFF
Noise filter ON
Noise filter OFF
Noise filter ON
Noise filter OFF
Noise filter ON
Figure 14-18. Format of Noise Filter Enable Register 0 (NFEN0)
Use of noise filter of R
SNFEN30
6
R/W
X
X
X
X
D3 pin.
D2 pin.
D1 pin.
D0 pin.
5
0
X
D3/P50/SEGx (78K0R/LF3: x = 30, 78K0R/LG3: x = 39, 78K0R/LH3: x = 53) pin
Use of noise filter of R
Use of noise filter of R
Use of noise filter of R
SNFEN20
4
X
X
2
C communication, by clearing the corresponding bit of
D2/P11/SI20/SDA20/INTP6 pin
D1/P14/SI10/SDA10/INTP4 pin
X
3
0
D0/P80/SI00/INTP9 pin
CHAPTER 14 SERIAL ARRAY UNIT
CLK
SNFEN10
) is synchronized with 2-clock match
2
1
0
SNFEN00
0
470