UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 1010

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
3rd Edition
Edition
Addition of <5> to 12.4.1 Single AMP Mode
Modification of Figure 13-1 Block Diagram of Voltage Reference
Modification of description in 13.3 (2) Analog reference voltage control register
(ADVRC)
Modification of Figure 13-3 Format of Analog Reference Voltage Control
Register (ADVRC)
Modification of <2> to <5> in 13.4.1 Reference voltage output mode
Addition of 13.5 Cautions for Voltage Reference
Addition of Note to 14.1.3 Simplified I
Modification of Figure 14-1 Block Diagram of Serial Array Unit 0
Modification of Figure 14-2 Block Diagram of Serial Array Unit 1
Modification of Note 2 in Figure 14-5 Format of Serial Clock Select Register m
(SPSm)
Modification of description of and addition of Note to Figure 14-7 Format of Serial
Communication Operation Setting Register mn (SCRmn) (1/3)
Addition of Caution 3 to Figure 14-8 Format of Serial Data Register mn (SDRmn)
Addition of Note to Figure 14-9 Format of Serial Status Register mn (SSRmn)
Modification of Figure 14-10 Format of Serial Flag Clear Trigger Register mn
(SIRmn)
Modification of Figure 14-26 Procedure for Stopping Master Transmission
Modification of Figure 14-27 Procedure for Resuming Master Transmission
Modification of Figure 14-28 Timing Chart of Master Transmission (in Single-
Transmission Mode)
Modification of Figure 14-30 Timing Chart of Master Transmission (in
Continuous Transmission Mode)
Modification of Figure 14-31 Flowchart of Master Transmission (in Continuous
Transmission Mode)
Modification of Figure 14-36 Timing Chart of Master Reception (in Single-
Reception Mode)
Modification of Figure 14-40 Procedure for Stopping Master
Transmission/Reception
Modification of Figure 14-41 Procedure for Resuming Master
Transmission/Reception
Modification of Figure 14-42 Timing Chart of Master Transmission/Reception (in
Single-Transmission/Reception Mode)
Modification of Figure 14-44 Timing Chart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode)
Modification of Figure 14-45 Flowchart of Master Transmission/Reception (in
Continuous Transmission/Reception Mode)
Modification of 14.5.4 Slave transmission and Note 1
Modification of Figure 14-48 Procedure for Stopping Slave Transmission
Modification of Figure 14-49 Procedure for Resuming Slave Transmission
Modification of Figure 14-50 Timing Chart of Slave Transmission (in Single-
Transmission Mode)
Modification of Figure 14-52 Timing Chart of Slave Transmission (in Continuous
Transmission Mode)
Description
2
C (IIC10, IIC20)
APPENDIX D REVISION HISTORY
CHAPTER 12
OPERATIONAL
AMPLIFIER
CHAPTER 13
VOLTAGE REFERENCE
CHAPTER 14 SERIAL
ARRAY UNIT
Chapter
(8/11)
1010