UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 306

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
6.7 Operation of Timer Array Unit as Independent Channel
6.7.1 Operation as interval timer/square wave output
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(1) Interval timer
(2) Operation as square wave output
The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals.
The interrupt generation period can be calculated by the following expression.
TOpq performs a toggle operation as soon as INTTMpq has been generated, and outputs a square wave with a
duty factor of 50%.
The period and frequency for outputting a square wave from TOpq can be calculated by the following expressions.
The valid edge of TIpq pin input signal, the valid edge of f
INTRTC1 can be selected as the count clock, in addition to CKm0 and CKm1. Consequently, the interval timer can
be operated, regardless of the f
When changing the clock selected as f
timer array units 0 and 1 (TAUS0, TAUS1) (TT0 = 00FFH, TT1 = 000FH) first.
Only in the case of SDIV=0, CCSmn=1 and TISmn=1, continuously use of TAUm is allowed, even when changing
CPU clock. However, the following limitation is existing.
• When changing CPU clock, source clock decrease/increase occurs as follows.
TCRmn operates as a down counter in the interval timer mode.
TCRmn loads the value of TDRmn at the first count clock after the channel start trigger bit (TSmn) is set to 1. If
MDmn0 of TMRmn = 0 at this time, INTTMmn is not output and TOpq is not toggled. If MDmn0 of TMRmn = 1,
INTTMmn is output and TOpq is toggled.
After that, TCRmn count down in synchronization with the count clock.
When TCRmn = 0000H, INTTMmn is output and TOpq is toggled at the next count clock. At the same time,
TCRmn loads the value of TDRmn again. After that, the same operation is repeated.
TDRmn can be rewritten at any time. The new value of TDRmn becomes valid from the next period.
Generation period of INTTMmn (timer interrupt) = Period of count clock × (Set value of TDRmn + 1)
• Period of square wave output from TOpq = Period of count clock × (Set value of TDRpq + 1) × 2
• Frequency of square wave output from TOpq = Frequency of count clock/{(Set value of TDRpq + 1) × 2}
Main clock → Subsystem clock (CSS = 0→1): −1 clock
Subsystem clock → Main clock (CSS = 1→0): +1 clock
CLK
frequency (main system clock, subsystem clock).
CLK
(changing the value of the system clock control register (CKC)), stop the
SUB
/2, the valid edge of f
CHAPTER 6 TIMER ARRAY UNIT
SUB/
4, or the valid edge of
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