UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 63

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
2.2.13 P120 to P124
external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock,
external clock input for main system clock, and external interrupt request input.
(1) Port mode
(2) Control mode
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
P120 function as an I/O port. P121 to P124 function as an input port. These pins also function as potential input for
The following operation modes can be specified in 1-bit units.
P120/INTP0/EXLVI
P121/X1
P122/X2/EXCLK
P123/XT1
P124/XT2
P120 functions as an I/O port. P120 can be set to input port or output port using port mode register 12 (PM12). Use
of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
P121 to P124 function as an input port.
P120 to P124 function as potential input for external low-voltage detection, connecting resonator for main system
clock, connecting resonator for subsystem clock, external clock input for main system clock, and external interrupt
request input.
(a) EXLVI
(b) X1, X2
(c) EXCLK
(d) XT1, XT2
(e) INTP0
Caution The function setting on P121 to P124 is available only once after the reset release. The port once
This is a potential input pin for external low-voltage detection.
These are the pins for connecting a resonator for main system clock.
This is an external clock input pin for main system clock.
These are the pins for connecting a resonator for subsystem clock.
This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and
falling edges) can be specified.
set for connection to an oscillator cannot be used as an input port unless the reset is performed.
(80 pins:
78F1501A, 78F1502A)
78K0R/LF3
μ
PD78F1500A,
(100 pins:
78F1504A, 78F1505A)
78K0R/LG3
μ
PD78F1503A,
√
√
√
√
√
CHAPTER 2 PIN FUNCTIONS
(128 pins:
78F1507A, 78F1508A)
78K0R/LH3
μ
PD78F1506A,
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