UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 875
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 875 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Instruction
16-bit
operation
Multiply
Group
2.
2. This number of clocks is for when the program is in the internal ROM (flash memory) area.
Mnemonic
ADDW
SUBW
CMPW
MULU
When the internal RAM area or SFR area is accessed, or for an instruction with no data access.
When the program memory area is accessed.
register (CKC).
AX, #word
AX, AX
AX, BC
AX, DE
AX, HL
AX, saddrp
AX, !addr16
AX, [HL+byte]
AX, ES:!addr16
AX, ES: [HL+byte]
AX, #word
AX, BC
AX, DE
AX, HL
AX, saddrp
AX, !addr16
AX, [HL+byte]
AX, ES:!addr16
AX, ES: [HL+byte]
AX, #word
AX, BC
AX, DE
AX, HL
AX, saddrp
AX, !addr16
AX, [HL+byte]
AX, ES:!addr16
AX, ES: [HL+byte]
X
Operands
Bytes
Table 30-5. Operation List (11/17)
3
1
1
1
1
2
3
3
4
4
3
1
1
1
2
3
3
4
4
3
1
1
1
2
3
3
4
4
1
Note 1 Note 2
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
2
2
1
Clocks
−
−
−
−
−
−
4
4
5
5
−
−
−
−
−
4
4
5
5
−
−
−
−
−
4
4
5
5
−
AX, CY ← AX + word
AX, CY ← AX + AX
AX, CY ← AX + BC
AX, CY ← AX + DE
AX, CY ← AX + HL
AX, CY ← AX + (saddrp)
AX, CY ← AX + (addr16)
AX, CY ← AX + (HL + byte)
AX, CY ← AX + (ES:addr16)
AX, CY ← AX + ((ES:HL) + byte)
AX, CY ← AX − word
AX, CY ← AX − BC
AX, CY ← AX − DE
AX, CY ← AX − HL
AX, CY ← AX − (saddrp)
AX, CY ← AX − (addr16)
AX, CY ← AX − (HL + byte)
AX, CY ← AX − (ES:addr16)
AX, CY ← AX − ((ES:HL) + byte)
AX − word
AX − BC
AX − DE
AX − HL
AX − (saddrp)
AX − (addr16)
AX − (HL + byte)
AX − (ES:addr16)
AX − ((ES:HL) + byte)
AX ← A × X
CPU
) selected by the system clock control
Operation
CHAPTER 30 INSTRUCTION SET
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Flag
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
875
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