UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 248

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
(1) CPU operating with internal high-speed oscillation clock (B) after reset release (A)
(2) CPU operating with high-speed system clock (C) after reset release (A)
(3) CPU operating with subsystem clock (D) after reset release (A)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(A) → (B)
(A) → (B) → (D)
Status Transition
Status Transition
(A) → (B) → (C)
(X1 clock: 2 MHz ≤ f
(A) → (B) → (C)
(X1 clock: 10 MHz < f
(A) → (B) → (C)
(external main clock)
Table 5-4 shows transition of the CPU clock and examples of setting the SFR registers.
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
(The CPU operates with the internal high-speed oscillation clock immediately after a reset release (B).)
Note The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release.
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
(Setting sequence of SFR registers)
2. FSEL = 1 when f
(Setting sequence of SFR registers)
CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Status Transition
manipulation instruction after reset release.
If a divided clock is selected and f
Setting Flag of SFR Register
X
Setting Flag of SFR Register
X
≤ 10 MHz)
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (1/6)
≤ 20 MHz)
CLK
> 10 MHz
SFR registers do not have to be set (default status after reset release).
EXCLK
OSCSELS
CLK
0
0
1
1
CMC Register
≤ 10 MHz, use with FSEL = 0 is possible even if f
CMC Register
OSCSEL
AMPHS1
1
1
1
0/1
Note 1
AMPH
Note
0
1
×
AMPHS0
SFR Register Setting
0/1
Register
MSTOP
CSC
CHAPTER 5 CLOCK GENERATOR
0
0
0
XTSTOP
Register
CSC
0
Register
OSMC
0/1
FSEL
1
Note 2
0
Note 2
Stabilization
Waiting for
Necessary
Oscillation
Register
checked
checked
checked
Must be
Must be
OSTC
not be
Must
X
> 10 MHz.
Register
MCM0
Register
CKC
1
1
1
CKC
CSS
1
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