UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 589

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
15.3 Registers Controlling Serial Interface IICA
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F00F0H
Serial interface IICA is controlled by the following eight registers.
(1) Peripheral enable register 0 (PER0)
(2) IICA control register 0 (IICCTL0)
Symbol
PER0
• Peripheral enable register 0 (PER0)
• IICA control register 0 (IICCTL0)
• IICA flag register (IICF)
• IICA status register (IICS)
• IICA control register 1 (IICCTL1)
• IICA low-level width setting register (IICWL)
• IICA high-level width setting register (IICWH)
• Port mode register 6 (PM6)
• Port register 6 (P6)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When serial interface IICA is used, be sure to set bit 4 (IICAEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution
This register is used to enable/stop I
IICCTL0 can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE, WTIM, and ACKE
bits while IICE bit = 0 or during the wait period. These bits can be set at the same time when the IICE bit is set
from “0” to “1”.
Reset signal generation clears this register to 00H.
Note 78K0R/LG3, 78K0R/LH3 only
IICAEN
RTCEN
<7>
When setting serial interface IICA, be sure to set IICAEN to 1 first. If IICAEN = 0, writing to a
control register of serial interface IICA is ignored, and, even if the register is read, only the
default value is read.
0
1
After reset: 00H
Stops supply of input clock.
• SFR used by serial interface IICA cannot be written.
• Serial interface IICA is in the reset status.
Supplies input clock.
• SFR used by serial interface IICA can be read/written.
DACEN
Figure 15-5. Format of Peripheral Enable Register 0 (PER0)
<6>
R/W
ADCEN
2
<5>
C operations, set wait timing, and set other I
Control of serial interface IICA input clock
IICAEN
<4>
Note
SAU1EN
<3>
CHAPTER 15 SERIAL INTERFACE IICA
SAU0EN
<2>
2
C operations.
TAU1EN
<1>
TAU0EN
<0>
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