UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 390

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Note
Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0).
Remarks 1. n = 0, 1
Address: FFFA5H (CKS0), FFFA6H (CKS1)
Symbol
CKSn
Setting an output clock exceeding 10 MHz is prohibited when 2.7 V ≤ V
V
DD
< 2.7 V is also prohibited.
2.
3.
2. f
3. f
If the selected clock (f
undefined.
To shift to STOP mode when the main system clock is selected (CSELn = 0), set PCLOEn = 0
before executing the STOP instruction. When the subsystem clock is selected (CSELn = 1),
PCLOEn = 1 can be set because the clock can be output in STOP mode.
MAIN
SUB
PCLOEn
PCLOEn
CSELn
: Subsystem clock frequency
: Main system clock frequency
<7>
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 9-2. Format of Clock Output Select Register n (CKSn)
Output disable (default)
Output enable
CCSn2
6
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MAIN
CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
CCSn1
or f
5
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
After reset: 00H
SUB
PCLBUZn output enable/disable specification
) stops during clock output (PCLOEn = 1), the output becomes
CCSn0
4
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R/W
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
CSELn
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
3
2
3
4
5
6
7
2
3
4
11
12
13
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz
2.44 kHz
1.22 kHz
610 Hz
PCLBUZn output clock selection
5 MHz
f
MAIN
CCSn2
DD
=
. Setting a clock exceeding 5 MHz at
2
5 MHz
2.5 MHz
625 kHz
4.88 kHz
2.44 kHz
1.22 kHz
10 MHz
1.25 MHz
32.768 kHz
16.384 kHz
8.192 kHz
4.096 kHz
2.048 kHz
1.024 kHz
10 MHz
512 Hz
256 Hz
f
MAIN
CCSn1
Note
1
=
Setting
prohibited
10 MHz
5 MHz
2.5 MHz
1.25 MHz
9.76 kHz
4.88 kHz
2.44 kHz
20 MHz
f
CCSn0
MAIN
0
Note
=
Note
390