UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 278
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 278 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(a) Start timing in interval timer mode
Cautions 1. Channel 5 of timer array unit 0 and channels 0 to 3 of timer array unit 1 of the 78K0R/LF3 can
Remark mn: Unit number + Channel number
<1> Writing 1 to TSmn sets TEmn = 1
<2> The write data to TSmn is held until count clock generation.
<3> TCRmn holds the initial value until count clock generation.
<4> On generation of count clock, the “TDRmn value” is loaded to TCRmn and count starts.
• Interval timer mode
• Event counter mode
• Capture mode
• One-count mode
• Capture & one-count mode
Table 6-4. Operations from Count Operation Enabled State to TCRmn Count Start
2. Channel 6 of timer array unit 0 of the 78K0R/LF3 can be set only to the interval mode and
3. Channels 0 to 3 of timer array unit 1 of the 78K0R/LG3 can be set only to the interval mode.
mn = 00 to 07, 10 to 13
Timer operation mode
one-count mode (when using as master).
be set only to the interval mode.
No operation is carried out from start trigger detection (TSmn=1) until count clock
generation.
The first count clock loads the value of TDRmn to TCRmn and the subsequent
count clock performs count down operation (see 6.3 (6) (a) Start timing in
interval timer mode).
Writing 1 to TSmn bit loads the value of TDRmn to TCRmn.
The subsequent count clock performs count down operation.
The external trigger detection selected by STSmn2 to STSmn0 bits in the
TMRmn register does not start count operation (see 6.3 (6) (b) Start timing in
event counter mode).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCRmn and the subsequent count clock
performs count up operation (see 6.3 (6) (c) Start timing in capture mode).
When TEmn = 0, writing 1 to TSmn bit sets the start trigger wait state.
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of TDRmn to TCRmn and the subsequent
count clock performs count down operation (see 6.3 (6) (d) Start timing in one-
count mode).
When TEmn = 0, writing 1 to TSmn bit sets the start trigger wait state.
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to TCRmn and the subsequent count clock
performs count up operation (see 6.3 (6) (e) Start timing in capture & one-
count mode).
Operation when TSmn = 1 is set
CHAPTER 6 TIMER ARRAY UNIT
278
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