UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 297

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UPD78F1506GF-GAT-AX

Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet

Specifications of UPD78F1506GF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
78K0R/Lx3
6.4.2 TOpq Pin Output Setting
start.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The following figure shows the procedure and status transition of TOpq out put pin from initial setting to timer operation
Remark
Remark
<1> The operation mode of timer output is set.
<2> The timer output signal is set to the initial status by setting TOpq.
<3> The timer output operation is enabled by writing 1 to TOEpq (writing to TOpq is disabled).
<4> The port I/O setting is set to output (see 6.3 (15) Port mode registers 1, 3, 5, 8).
<5> The timer operation is enabled (TSpq = 1).
• TOMpq bit (0: Toggle mode, 1: Combination operation mode)
• TOLpq bit (0: Forward output, 1: Reverse output)
Timer alternate-function pin
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
<3> 78K0R/LH3:
<1> 78K0R/LF3:
<2> 78K0R/LG3:
Figure 6-27. Status Transition from Timer Output Setting to Operation Start
• p = 0, q = 0 to 4, 7 (q = 0, 2, 4 for master channel)
• p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel)
• p = 0, q = 0 to 7 (q = 0, 2, 4, 6 for master channel)
• p = 1, q = 0 to 3 (q = 0, 2 for master channel)
Timer output signal
q < r ≤ 7 (where r is a consecutive integer greater than q)
q < r ≤ 7 (where r is a consecutive integer greater than q)
q < r ≤ 7 (where r is a consecutive integer greater than q)
q < r ≤ 3 (where r is a consecutive integer greater than q)
TCRpq
TOEpq
(Counter)
TOpq
<1> Set the TOMpq
Write operation enabled period to TOpq
Set the TOLpq
Undefined value (FFFFH after reset)
<2> Set the TOpq <3> Set the TOEpq
Hi-Z
Write operation disabled period to TOpq
<4> Set the port to
output mode
CHAPTER 6 TIMER ARRAY UNIT
<5> Timer operation start
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