UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 1008

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
3rd Edition
2nd Edition
Edition
(3) Serial interface: IICA in AC Characteristics
• Modification of Table
(3) Voltage Reference in Analog Characteristics
• Addition of Remark
(4) D/A Converter in Analog Characteristics
• Addition of Gain error (EG)
(2) Internal voltage boosting method in LCD Characteristics
• Modification of LCD output voltage variation range
(3) Capacitor split method in LCD Characteristics
• Modification of V
Addition of chapter
Addition of chapter
DF781508, QB-78K0RLX3: Under development → Under mass production
Addition of QB-Programmer Programming GUI Operation User’s Manual to
Related Documents
Modification of 1.1 Features
Modification of 2.2.21 RESET and 2.2.22 REGC
Addition of Note 1 to Figure 3-1 Memory Map (
Addition of Note 1 to Figure 3-2 Memory Map (
Addition of Note 1 to and modification of Figure 3-3 Memory Map (
78F1505, 78F1508)
Modification of description in 3.1.1 (1) Vector table area
Modification of 3.1.2 Mirror area
Modification of description in and addition of Cautions 1, 2 to 3.1.3 Internal data
memory space
Modification of Figure 3-7 Correspondence Between Data Memory and
Addressing (
Addition of Cautions 2, 3 to 3.2.1 (3) Stack pointer (SP)
Modification of Figure 4-1 Block Diagram of P00 and P01
Modification of Figure 4-2 Block Diagram of P02
Modification of Figure 5-6 Format of System Clock Control Register (CKC)
Modification of <2> in 5.6.2 (2) Example of setting procedure when using internal
high-speed oscillation clock as CPU/peripheral hardware clock
Modification of Table 5-4 CPU Clock Transition and SFR Register Setting
Examples
Modification of Table 5-8 Maximum Number of Clocks Required in f
Table 5-9 Maximum Number of Clocks Required in f
Modification of Note 1 in Figure 6-6 Format of Timer Clock Select Register m
(TPSm)
Modification of Figure 6-7 Format of Timer Mode Register mn (TMRmn) (1/4)
Addition of description of Event counter mode to Table 6-4 Operations from Count
Operation Enabled State to TCRmn Count Start
Addition of description to 6.4.3
TOp,TOEp,TOLp, and TOMp during timer operation
μ
PD78F1502, 78F1505, 78F1508)
LC0
voltage
Description
(1)
Changing values set in registers
μ
μ
PD78F1500, 78F1503, 78F1506)
PD78F1501, 78F1504, 78F1507)
MAINC
↔f
SUBC
μ
PD78F1502,
IH
APPENDIX D REVISION HISTORY
↔f
MX
and
CHAPTER 31
ELECTRICAL
SPECIFICATIONS
(TARGET)
(continuation)
APPENDIX A
DEVELOPMENT
TOOLS
APPENDIX B
REVISION HISTORY
Throughout
INTRODUCTION
CHAPTER 1 OUTLINE
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5 CLOCK
GENERATOR
CHAPTER 6 TIMER
ARRAY UNIT
Chapter
(6/11)
1008