UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 1005

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
2nd Edition
Edition
Modification of Table 12-1 Configuration of Operational Amplifiers
Addition of (1) Peripheral enable register 0 (PER0)
Modification of Table 12-2 Setting Functions of ANI0/AMP0-/P20,
ANI2/AMP0+/P22, ANI3/AMP1-/P23, ANI5/AMP1+/P25, ANI6/AMP2-/P26, and
ANI8/AMP2+/P150 Pins Table 12-3 Setting Functions of ANI1/AMP0O/P21,
ANI4/AMP1O/P24, and ANI7/AMP2O/P27 Pins, and Table 12-5 Setting Functions
of ANI15/AV
Addition of <1> to 12.4.1 Single AMP Mode
Modification of Table 13-1 Configuration of Voltage Reference
Modification of Figure 13-1 Block Diagram of Voltage Reference
Addition of (1) Peripheral enable register 0 (PER0)
Modification of (2) A/D reference voltage control register (ADVRC)
Modification of 13.4.1 Reference voltage output mode
Modification of Figure 14-4 Format of Peripheral Enable Register 0 (PER0)
Modification of Caution 2 in Figure 14-5 Format of Serial Clock Select Register m
(SPSm)
Modification of Figure 14-22 Peripheral Enable Register 0 (PER0) Setting When
Stopping the Operation by Units
Modification of Caution in Figure 14-25 Initial Setting Procedure for Master
Transmission
Modification of Caution in Figure 14-29 Flowchart of Master Transmission (in
Single-Transmission Mode)
Modification of Caution in Figure 14-31 Flowchart of Master Transmission (in
Continuous Transmission Mode)
Modification of Caution in Figure 14-33 Initial Setting Procedure for Master
Reception
Modification of Caution in Figure 14-37 Flowchart of Master Reception (in Single-
Reception Mode)
Modification of Caution in Figure 14-39 Initial Setting Procedure for Master
Transmission/Reception
Modification of Caution in Figure 14-43 Flowchart of Master
Transmission/Reception (in Single- Transmission/Reception Mode)
Modification of Caution in Figure 14-45 Flowchart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode)
Modification of Caution in Figure 14-47 Initial Setting Procedure for Slave
Transmission
Modification of Caution in Figure 14-51 Flowchart of Slave Transmission (in
Single-Transmission Mode)
Modification of Caution in Figure 14-53 Flowchart of Slave Transmission (in
Continuous Transmission Mode)
Modification of Caution in Figure 14-55 Initial Setting Procedure for Slave
Reception
Modification of Caution in Figure 14-59 Flowchart of Slave Reception (in Single-
Reception Mode)
Modification of Caution in Figure 14-61 Initial Setting Procedure for Slave
Transmission/Reception
Modification of Caution in Figure 14-65 Flowchart of Slave
Transmission/Reception (in Single- Transmission/Reception Mode)
REFM
/P157 Pin
Description
APPENDIX D REVISION HISTORY
CHAPTER 12
OPERATIONAL
AMPLIFIER
CHAPTER 13
VOLTAGE REFERENCE
CHAPTER 14 SERIAL
ARRAY UNIT
Chapter
(3/11)
1005