UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 966

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Clock
generator
Function
CMC: Clock
operation mode
control register
CSC: Clock
operation status
control register
OSTC:
Oscillation
stabilization time
counter status
register
Details of
Function
The XT1 oscillator is designed as a low-gain circuit for achieving low-power
consumption. Note the following points when designing the XT1 oscillator.
After reset release, set the clock operation mode control register (CMC) before
starting X1 oscillation as set by MSTOP or XT1 oscillation as set by XTSTOP.
To start X1 oscillation as set by MSTOP, check the oscillation stabilization time of the
X1 clock by using the oscillation stabilization time counter status register (OSTC).
Do not stop the clock selected for the CPU peripheral hardware clock (f
CSC register.
The setting of the flags of the register to stop clock oscillation (invalidate the external
clock input) and the condition before clock oscillation is to be stopped are as follows.
After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. In the following cases, set the oscillation stabilization time of OSTS to
the value greater than the count value which is to be checked by the OSTC register
after the oscillation starts.
• If the X1 clock starts oscillation while the internal high-speed oscillation clock or
• If the STOP mode is entered and then released while the internal high-speed
• The pins and circuit board include parasitic capacitance. Therefore, confirm that
• When low-consumption oscillation or super-low-consumption oscillation is
• Keep the wiring length between the XT1 and XT2 pins and resonator as short as
• Configure the circuit board by using material with little parasitic capacitance and
• Place a ground pattern that has the same potential as V
• Do not cross the signal lines between the XT1 and XT2 pins and the resonator
• Moisture absorption by the circuit board and condensation on the board in a
• Coat the surface of the circuit board by using material that does not generate
subsystem clock is being used as the CPU clock.
oscillation clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after the STOP mode is released.)
there are no problems by performing oscillation evaluation on the circuit board to
be actually used.
selected, lower power consumption than when selecting normal oscillation can be
achieved.
perform sufficient oscillation evaluation of the resonator to be used for XT1
oscillation before using the resonator.
possible and parasitic capacitance and wire resistance as small as possible. This
is particularly important when super-low-consumption oscillation (AMPHS1 = 1) is
selected.
wire resistance.
XT1 oscillator.
with other signal lines. Do not route the signal lines near a signal line through
which a high fluctuating current flows.
highly humid environment may cause the impedance between the XT1 and XT2
pins to drop and disable oscillation. When using the circuit board in such an
environment, prevent the circuit board from absorbing moisture by taking
measures such as coating the circuit board.
capacitance or leakage between the XT1 and XT2 pins.
However, in this case, the XT1 oscillation margin is reduced, so
Cautions
APPENDIX C LIST OF CAUTIONS
SS
(if possible) around the
CLK
) with the
pp.217,
218
p.218
p.219
p.219
p.219
p.220
p.220
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