UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 581

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UPD78F1506GF-GAT-AX

Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet

Specifications of UPD78F1506GF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
78K0R/Lx3
Notes 1. The SE1 register is a read-only status register which is set using the SS1 and ST1 registers.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Remark X: Don’t care
SE11
0
1
Note1
2. When channel 1 of unit 1 is set to UART2 reception, this pin becomes an RxD2 function pin. In this case, set
3. This pin can be set as a port function pin.
4. When using UART2 transmission and reception in a pair, set channel 0 of unit 1 to UART2 transmission (refer to
5. The SMR10 register of channel 0 of unit 1 must also be set during UART2 reception. For details, refer to 14.5.2
Table 14-10. Relationship between register settings and pins (Channel 1 of unit 1: UART2 reception)
channel 0 of unit 1 to operation stop mode or UART2 transmission (refer to Table 14-9).
When channel 0 of unit 1 is set to CSI20 or IIC20, this pin cannot be used as an RxD2 function pin. In this case,
set channel 1 of unit 1 to operation stop mode.
Table 14-9).
(1) Register setting.
MD112
0
0
MD111
1
1
TXE11
0
0
RXE11
0
1
PM11
×
Note3
1
Note2
P11
×
Note3
×
Note2
CHAPTER 14 SERIAL ARRAY UNIT
stop mode
Operation
Operation
reception
UART2
Note4, 5
mode
SI20/SDA20/INTP6/P11
SI20/SDA20/RxD2/
INTP6/P11
Pin Function
RxD2
Note2
581

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