UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 789

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0R/Lx3
Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware
(2) STOP mode release
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
High-speed system
clock (external clock
input) is selected as
CPU clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
Note
The STOP mode can be released by the following two sources.
High-speed system
clock (X1 oscillation)
High-speed system
clock (external clock
input)
Internal high-speed
oscillation clock
Figure 21-5. Operation Timing When STOP Mode Is Released (When Unmasked Interrupt Request
2. To stop the internal low-speed oscillation clock in the STOP mode, use an option byte to stop the
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
4. The STOP instruction cannot be executed when the CPU operates on the 20 MHz internal high-speed
When the oscillation stabilization time set by OSTS is equal to or shorter than 61
retained to a maximum of "61
for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart
the peripheral hardware.
watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of 000C0H = 0), and then
execute the STOP instruction.
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the internal
high-speed oscillation clock before the next execution of the STOP instruction. Before changing the
CPU clock from the internal high-speed oscillation clock to the high-speed system clock (X1
oscillation) after the STOP mode is released, check the oscillation stabilization time with the
oscillation stabilization time counter status register (OSTC).
oscillation clock. Be sure to execute the STOP instruction after shifting to internal high-speed
oscillation clock operation.
STOP mode
STOP mode release
Wait for oscillation accuracy stabilization
(oscillation stabilization time set by OSTS)
μ
s + wait time."
Supply of the CPU clock is stopped (about 23.3 to 30.7 μs)
Supply of the CPU clock is stopped (about 23.3 to 30.7 μs)
HALT status
Internal high-speed
Wait (2 clocks)
Wait (1 clock)
Is Generated)
oscillation clock
Note
Clock switched by software
Clock switched by software
CHAPTER 21 STANDBY FUNCTION
High-speed system clock
High-speed system clock
High-speed system clock
μ
s, the HALT status is
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