UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 991

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Standby
function
Reset
function
Function
OSTS:
Oscillation
stabilization time
select register
STOP mode
Block diagram of
reset function
Watchdog timer
overflow
RESF: Reset
control flag
register
Details of
Function
−
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
Because the interrupt request signal is used to clear the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset,
the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the
HALT mode immediately after execution of the STOP instruction and the system
returns to the operating mode as soon as the wait time set using the oscillation
stabilization time select register (OSTS) has elapsed.
The STOP instruction cannot be executed when the CPU operates on the 20 MHz
internal high-speed oscillation clock. Be sure to execute the STOP instruction after
shifting to internal high-speed oscillation clock operation.
To use the peripheral hardware that stops operation in the STOP mode, and the
peripheral hardware for which the clock that stops oscillating in the STOP mode after
the STOP mode is released, restart the peripheral hardware.
To stop the internal low-speed oscillation clock in the STOP mode, use an option
byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0
(WDSTBYON) of 000C0H = 0), and then execute the STOP instruction.
To shorten oscillation stabilization time after the STOP mode is released when the
CPU operates with the high-speed system clock (X1 oscillation), temporarily switch
the CPU clock to the internal high-speed oscillation clock before the next execution
of the STOP instruction. Before changing the CPU clock from the internal high-
speed oscillation clock to the high-speed system clock (X1 oscillation) after the
STOP mode is released, check the oscillation stabilization time with the oscillation
stabilization time counter status register (OSTC).
For an external reset, input a low level for 10
(To perform an external reset upon power application, a low level of at least 10
must be continued during the period in which the supply voltage is within the
operating range (V
During reset input, the X1 clock, XT1 clock, internal high-speed oscillation clock, and
internal low-speed oscillation clock stop oscillating. External main system clock input
becomes invalid.
When the STOP mode is released by a reset, the RAM contents in the STOP mode
are held during reset input.
When reset is effected, port pin P140 is set to low-level output and other port pins
become high-impedance, because each SFR and 2nd SFR are initialized.
An LVI circuit internal reset does not reset the LVI circuit.
A watchdog timer internal reset resets the watchdog timer.
Do not read data by a 1-bit memory manipulation instruction.
Do not make a judgment based on only the read value of the RESF register 8-bit
data, because bits other than TRAP, WDRF, and LVIRF become undefined.
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, LVIRF
flag may become 1 from the beginning depending on the power-on waveform.
DD
≥ 1.8 V)).
Cautions
μ
s or more to the RESET pin
APPENDIX C LIST OF CAUTIONS
μ
s
p.780
p.787
pp.787
, 789
p.789
p.789
p.789
p.793
p.793
p.793
p.793
p.794
p.795
p.802
p.802
p.802
Page
(31/39)
991