UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 329

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
Remark
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
TAU
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
TAU stop
Figure 6-56. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used
78K0R/LF3: p = 0, pq = 00 to 04, 07
78K0R/LG3: p = 0, pq = 00 to 07
78K0R/LH3: p = 0, 1, pq = 00 to 07, 10 to 13
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
Sets the TAU0EN or TAU1EN bits of the PER0 register
to 1.
Sets the TPSp register.
Sets the TMRpq register (determines operation mode of
channel).
Clears TOEpq to 0 and stops operation of TOpq.
Sets the TSpq bit to 1.
Detects TIpq pin input count start valid edge.
Set value of the TDRpq register can be changed.
The TCRpq register can always be read.
The TSRpq register is not used.
Set values of TMRpq, TOMp, TOLp, TOp, and TOEp
registers cannot be changed.
The TTpq bit is set to 1.
The TAU0EN or TAU1EN bits of PER0 register is cleared
to 0.
Determines clock frequencies of CKp0 and CKp1.
The TSpq bit automatically returns to 0 because it is a
trigger bit.
TTpq bit automatically returns to 0 because it is a
trigger bit.
Software Operation
Channel stops operating.
(Clock is supplied and some power is consumed.)
TEpq = 1, and the TIpq pin start edge detection wait
status is set.
Clears TCRpq to 0000H and starts counting up.
When the TIpq pin start edge is detected, the counter
(TCRpq) counts up from 0000H. If a capture edge of the
TIpq pin is detected, the count value is transferred to
TDRpq and INTTMpq is generated.
If an overflow occurs at this time, the OVFpq bit of the
TSRpq register is set; if an overflow does not occur, the
OVFpq bit is cleared. TCRpq stops the count operation
until the next TIpq pin start edge is detected.
Power-off status
Power-on status. Each channel stops operating.
TEpq = 0, and count operation stops.
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
TCRpq holds count value and stops.
The OVFpq bit of the TSRpq register is also held.
All circuits are initialized and SFR of each channel is
also initialized.
CHAPTER 6 TIMER ARRAY UNIT
Hardware Status
329