UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 676

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Symbol
Address: F0080H
PFALL
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Cautions 1. The VLCD setting is valid only when the voltage boost circuit is operating.
Note 78K0R/LG3, 78K0R/LH3 only
(5)
Port function register (PFALL)
This register sets whether to use pins P50 to P57, P90 to P97, P100 to P102, and P140 to P147 as port pins
(other than segment output pins) or segment output pins.
PFALL is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PFALL to 00H.
Remark The port pins to be used alternatively with the segment output pins vary, depending on the product.
PF14H
PF14L
PF9H
PF10
PF9L
7
0
0
1
0
1
0
1
0
1
0
1
2. Bits 5 to 7 must be set to 0.
3. Be sure to change the VLCD value after having stopped the operation of the voltage boost circuit
4. These values above may change after device evaluation.
5. To use the internal voltage boosting method, specify the reference voltage by using the VLCD
(VLCON = 0).
register (or perform a reset to use the default value of the reference voltage), wait for the reference
voltage setup time (2 ms (min.)), and then set VLCON to 1.
After reset
• 78K0R/LF3:
• 78K0R/LG3:
• 78K0R/LH3:
Used the P144 to P147 pins as port (other than segment output)
Used the P144 to P147 pins as segment output
Used the P140 to P143 pins as port (other than segment output)
Used the P140 to P143 pins as segment output
Used the P100 to P102 pins as port (other than segment output)
Used the P100 to P102 pins as segment output
Used the P94 to P97 pins as port (other than segment output)
Used the P94 to P97 pins as segment output
Used the P90 to P93 pins as port (other than segment output)
Used the P90 to P93 pins as segment output
PF14H
:
6
00H
Figure 16-6. Format of Port Function Register (PFALL) (1/2)
R/W
P50 to P57, P90 to P92, P100, P140 to P147
P50 to P57, P90 to P97, P100, P140 to P147
P50 to P57, P90 to P97, P100 to P102, P140 to P147
PF14L
5
Port/segment outputs specification of the P144 to P147 pins
Port/segment outputs specification of the P140 to P143 pins
Port/segment outputs specification of the P100 to P102 pins
Port/segment outputs specification of the P94 to P97 pins
Port/segment outputs specification of P90 to P93 pins
PF10
4
PF9H
3
Note
CHAPTER 16 LCD CONTROLLER/DRIVER
PF9L
2
PF5H
1
PF5L
0
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