UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 684

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(2) Internal voltage boosting method
(3) Capacitor spli
<1> Set the internal voltage boosting method via the MDSET0 and MDSET1 bits (bits 4 and 5 of the LCDMD
<2> To use segment output only pins, use the SEGEN register to enable segment output to them.
<3> Set the display data in LCD display RAM.
<4> Set the number of time slices and the bias mode via the LCDM0 to LCDM2 bits (bits 0 to 2 of the LCDM
<5> Select the display data area via the LCDSEL and BLON bits (bits 3 and 4 of the LCDM register).
<6> Set the LCD source clock and LCD clock via the LCDC0 register.
<7> Set the reference voltage (adjust the contrast) via the VLCD register.
<8> Wait for the reference voltage setup time (2 ms (min.)) after setting of the VLCD register.
<9> Set (VLCON = 1) the VLCON bit (bit 5 of the LCDM register) to start the voltage boost circuit operation.
<10> Wait for the voltage boost wait time after setting of VLCON (see CHAPTER 31 ELECTRICAL
<11> Set (SCOC = 1) the SCOC bit (bit 6 of the LCDM register).
<12> Start output corresponding to each data memory by setting (LCDON = 1) the LCDON bit (bit 7 of the LCDM
Caution When stopping the operation of the voltage boost circuit, be sure to set SCOC and LCDON to 0
<1> Set the capacitor split method via the MDSET0 and MDSET1 bits (bits 4 and 5 of the LCDMD register)
<2> To use segment output only pins, use the SEGEN register to enable segment output to them.
<3> Set the display data in LCD display RAM.
<4> Set the number of time slices and the bias mode via the LCDM0 to LCDM2 bits (bits 0 to 2 of the LCDM
<5> Select the display data area via the LCDSEL and BLON bits (bits 3 and 4 of the LCDM register).
<6> Set the LCD source clock and LCD clock via the LCDC0 register.
<7> Set (VLCON = 1) the VLCON bit (bit 5 of the LCDM register) to start the voltage reduction circuit operation.
<8> Wait for the voltage capacitor split wait time after setting of VLCON (see CHAPTER 31 ELECTRICAL
register) (MDSET0 = 1, MDSET1 = 0).
To use segment output pins, which are alternatively used with port pins, use the PFALL register to set them
to segment output. In addition, to use the segment output pins, which are alternatively used with the TI04,
TI02, and RxD3 pins, use the ISC register to disable input to the Schmitt trigger buffer.
register).
(Only 1/3 bias mode and 1/4 bias mode can be set for the internal voltage boost method.)
SPECIFICATIONS).
Non-selected waveforms are output from all the segment and common pins, and the non-display status is
entered.
register).
(MDSET0 = 0, MDSET1 = 1).
To use segment output pins, which are alternatively used with port pins, use the PFALL register to set them
to segment output. In addition, to use the segment output pins, which are alternatively used with the TI04,
TI02, and RxD3 pins, use the ISC register to disable input to the Schmitt trigger buffer.
register).
(Only 1/3 bias mode can be set for the capacitor split method)
SPECIFICATIONS).
• When setting Static, 2-time-slice, 3-time-slice, or 4-time-slice → Go to step <5>
• When setting 8-time-slice → Go to step <6>
before setting VLCON to 0.
t
method
CHAPTER 16 LCD CONTROLLER/DRIVER
684