UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 228

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0R/Lx3
(8) Operation speed mode control register (OSMC)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
This register is used to control the step-up circuit of the flash memory for high-speed operation.
If the microcontroller operates at a low speed with a system clock of 10 MHz or less, the power consumption can be
lowered by setting this register to the default value, 00H.
OSMC can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F00F3H
Symbol
OSMC
Cautions 1. Write “1” to FSEL before the following two operations.
RTCLPC
FLPC
RTCLPC
0
1
0
0
1
1
Figure 5-9. Format of Operation Speed Mode Control Register (OSMC)
7
After reset: 00H
6. The HALT mode current when operating on the subsystem clock can be reduced by
7. Once FLPC has been set from 0 to 1, setting it back to 0 from 1 other than by reset is
2. The CPU waits (140.5 clock (f
3. To increase f
4. Confirm that the clock is operating at 10 MHz or less before setting FSEL = 0.
5. To shift to STOP mode while V
8. When setting FSEL to “1”, do so while RMC = 00H.
Enables subsystem clock supply to peripheral functions.
(See Table 21-1 Operating Statuses in HALT Mode (2/3) for the peripheral functions whose
operations are enabled.)
Stops subsystem clock supply to peripheral functions except real-time counter, clock
output/buzzer output, and LCD controller/driver.
• Changing the clock prior to dividing f
• Operating the DMA controller.
Interrupt requests issued during a wait will be suspended.
However, counting the oscillation stabilization time of f
CPU is waiting.
more clocks have elapsed.
setting RTCLPC to 1. However, the clock cannot be supplied to peripheral functions
except the real-time counter in the subsystem clock HALT mode. Set bit 7 (RTCEN)
of PER0 to 1 and bits 0 to 6 of PER0 to 0 before setting the subsystem clock HALT
mode.
prohibited.
When setting FLPC to “1”, do so while RMC = 5AH.
less.
FSEL
0
1
0
1
6
0
Operates at a frequency of 10 MHz or less (default).
Operates at a frequency higher than 10 MHz.
Operates at a frequency of 1 MHz.
Setting prohibited
R/W
CLK
5
0
to 10 MHz or higher, set FSEL to “1”, then change f
Setting in subsystem clock HALT mode
4
0
CLK
DD
)) when “1” is written to the FSEL bit.
f
≤ 2.7 V, set FSEL = 0 after setting f
CLK
frequency selection
3
0
CLK
to a clock other than f
CHAPTER 5 CLOCK GENERATOR
2
0
X
can continue even while the
FLPC
1
IH
.
CLK
CLK
FSEL
to 10 MHz or
0
after two or
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