UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 253

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UPD78F1506GF-GAT-AX

Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet

Specifications of UPD78F1506GF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
78K0R/Lx3
(13) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
(14) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(B) → (E)
(C) → (F)
(D) → (G)
(J) → (K)
(B) → (H)
(C) → (I)
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
• HALT mode (K) set while CPU is operating with 20 MHz internal high-speed oscillation clock (J)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
Remark (A) to (K) in Table 5-4 correspond to (A) to (K) in Figure 5-15.
Status Transition
Status Transition
Table 5-4. CPU Clock Transition and SFR Register Setting Examples (6/6)
(Setting sequence)
In X1 oscillation
External main
system clock
Executing HALT instruction
Stopping peripheral
functions that cannot
operate in STOP
mode
Sets the OSTS
register
Setting
Setting
CHAPTER 5 CLOCK GENERATOR
Executing STOP
instruction
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