UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 951

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
APPENDIX B REGISTER INDEX
APPENDIX B REGISTER INDEX
B.1 Register Index (In Alphabetical Order with Respect to Register Names)
[A]
A/D converter mode register (ADM) ........................................................................................................................... 397
A/D converter mode register 1 (ADM1) ...................................................................................................................... 400
A/D port configuration register (ADPC) ...................................................................................................... 200, 404, 434
Alarm hour register (ALARMWH) ............................................................................................................................... 366
Alarm minute register (ALARMWM) ........................................................................................................................... 366
Alarm week register (ALARMWW) ............................................................................................................................. 367
Analog input channel specification register (ADS)...................................................................................................... 403
Analog reference voltage control register (ADVRC) ........................................................................................... 401, 440
[B]
Background event control register (BECTL)............................................................................................................... 844
BCD correction result register (BCDADJ)................................................................................................................... 859
[C]
Clock operation mode control register (CMC) ............................................................................................................ 216
Clock operation status control register (CSC) ............................................................................................................ 218
Clock output selection register 0 (CKS0).................................................................................................................... 389
Clock output selection register 1 (CKS1).................................................................................................................... 389
[D]
D/A conversion value setting register 0 (DACS0)....................................................................................................... 427
D/A conversion value setting register 1 (DACS1)....................................................................................................... 427
D/A conversion value setting register W0 (DACSW0) ................................................................................................ 427
D/A conversion value setting register W1 (DACSW1) ................................................................................................ 427
D/A converter mode register (DAM) ........................................................................................................................... 426
Day count register (DAY) ........................................................................................................................................... 362
DMA byte count register n (DBCn) ............................................................................................................................. 725
DMA mode control register n (DMCn) ........................................................................................................................ 726
DMA operation control register n (DRCn)................................................................................................................... 728
DMA RAM address register n (DRAn)........................................................................................................................ 724
DMA SFR address register n (DSAn)......................................................................................................................... 723
[E]
8-bit A/D conversion result register (ADCRH) .................................................................................................... 395, 402
External interrupt falling edge enable register (EGN0) ............................................................................................... 765
External interrupt falling edge enable register (EGN1) ............................................................................................... 765
External interrupt rising edge enable register (EGP0) ................................................................................................ 765
External interrupt rising edge enable register (EGP1) ................................................................................................ 765
[H]
Hour count register (HOUR) ....................................................................................................................................... 361
[I]
IICA control register 0 (IICCTL0) ................................................................................................................................ 589
R01UH0004EJ0401 Rev.4.01
951
Jul 2, 2010